Reset signals may be used to force flip-flops inside a chip to a known state. In instances where flip-flops are used to make clock-divider circuits, resetting these flip-flops may be problematic because the clocks that are normally outputs of the clock divider circuit may not run during reset. The reason may be that the flip-flops are held in a certain state the entire time that the reset signal is asserted. Without the clock running, some portions of the chip may not get properly initialized. For example, a pipeline design may rely on the clock to be running in order for cleared data to get clocked all the way through the pipeline.
In conventional chips, there may be three common scenarios with regard to clock dividers. There may be clock divider flip-flops that do not use any sort of reset signal to get them into a known state. In silicon, the flip-flops may start in a particular state, either 0 or 1. The clock output from the divider may then run. However, since the flip-flops can come up in either state, the phase of the resulting clock is not predictable. In certain situations, for example in functional test vectors, it is problematic to have the phase of the clock not be repeatable because the resulting overall behavior of the chip will not be repeatable. This may cause vectors to mismatch because the shifted clock phase results in actual chip behavior being time-shifted from the expected behavior.
The clock divider flip-flops may also use the same main reset signal as a chip reset signal. In this scenario, the clocks generated by the clock divider do not run during reset and this may be problematic for a variety of reasons. For example, a pipeline design may be configured so that it is not reset directly, but gets reset or cleared when known data from flip-flops, for example, gets clocked through the pipeline during reset. As a result, at the end of a reset, the output of the pipeline is in a known state, so any circuitry which uses this data will have valid data immediately after reset is de-asserted. However, if the clock is not running, then the known data may not get clocked through the pipeline, and any circuitry which uses the output of the pipeline may receive invalid data immediately after reset is de-asserted. The clock may not run because the clock divider flip-flops are being held in reset the entire time the chip's reset is asserted.
In addition, the clock divider reset may be generated via a pin of the chip, and the reset utilized by the rest of the chip may be a delayed version of the main reset input. In this scenario the clocks may not be allowed to run while the chip's main internal reset is still asserted. However, it means that the main portion of the chip may come out of reset significantly after the reset input to the chip is de-asserted. This may cause timing problems if the chip is coupled to other devices. For example, if the chip has a PCI interface, then an external PCI master on the board may start a transaction immediately after the board reset is de-asserted. However, since the main internal reset in the chip is delayed, the chip's PCI interface will still be dead or invalid because it is being held in reset and it may miss this initial transaction.
Further limitations and disadvantages of conventional and traditional approaches will become apparent to one of skill in the art, through comparison of such systems with some aspects of the present invention as set forth in the remainder of the present application with reference to the drawings.